EN

Photonic IP and optical engines

Two halves of one optical path

The interface that moves memory traffic onto light, and the packaged engines that carry it from inside the package to the far end of the rack.

Memory disaggregation over photonic interconnect

Copper sets the distance at which memory stops being local. Moving the link to light changes that distance, and with it the shape of the rack.

A compute die connected over three optical links to a pool of three shared memory stacks ComputeACCELERATOROPTICALHBM4HBM4HBM4SHARED POOL

AOPHBM4

Our photonic HBM4 interface. It takes high-bandwidth memory traffic off copper and onto an optical link, so the memory a processor addresses no longer has to sit within a few centimetres of it.

Scale-up

Disaggregated memory pools shared across the accelerators in a single rack. Capacity is provisioned once for the rack rather than over-provisioned node by node for the worst-case job.

Scale-out

Optical die-to-die and die-to-memory reach beyond the package: from co-packaged optics on the substrate out to rack-to-rack links, on one optical path.

Four places to put the optics

The engine moves closer to the die at each step. Electrical reach shortens, density rises, and the integration cost moves earlier in the build.

  1. Front panel

    XPO

    Extra-dense pluggable optics. Density at the faceplate without moving the optics inside the package, so the module stays field-serviceable.

  2. On the substrate

    NPO

    Near-package optics, with engines beside the ASIC rather than in its package. The step between pluggable and fully co-packaged.

  3. In the package

    CPO

    Co-packaged optics. The optical engine shares a package with the switch or accelerator die, cutting electrical reach to millimetres.

  4. Multi-vendor

    Open CPX

    An open co-packaged form factor. The same integration as CPO, with the optical engine kept interoperable across suppliers rather than tied to one.

Built on the platforms you already qualify

Our solutions span GlobalFoundries, Samsung, and TSMC platforms, with silicon-proven delivery at 2nm on both Samsung and TSMC.

Request an IP factsheet

Tell us the interface and the reach, and we will send the detail that matters for your programme.

Contact us